Yuvan004

Area-Efficient Arithmetic Expression Evaluation Using Deeply Pipelined Floating-Point Cores Using VHDL.

Description
It has become possible to implement floating-point cores on field-programmable gate arrays (FPGAs) to provide acceleration for the myriad applications that require high-performance floating-point arithmetic. To achieve high clock rates, floating-point cores for FPGAs must be deeply pipelined.